The present invention relates to output buffers of integrated digital systems, and, in particular, to a pre-charging circuit for speeding up the switching of an output buffer without inducing excessive switching noise on the supply lines of the integrated circuit.
Many integrated digital systems processing and/or handling digital data streams are provided with one, or more often, with an array of output buffers for driving the lines of a data bus. The switching of an output buffer produces disturbances or switching noise that propagates through the power supply rails. Circuits upstream of the output buffers may be negatively conditioned by such a switching noise coming from the power supply rails of the integrated circuit, and may produce synchronization errors and/or spurious switching.
In fact, the supply voltage, commonly generated and regulated externally and applied to the integrated circuit (IC) may be subjected within the chip to variations due to internal resistive drops proportional to the absorbed current, and to inductive effects inversely proportional to the rise time of the step function of absorbed current. Both these effects contribute to the supply noise.
Switching noise is always present, but is particularly intense during the charging phase of new output data. In these phases each output buffer absorbs a relatively large current to charge the external load capacitance. This causes a noise spike that may slow down propagation of the signals inside the integrated circuit and/or cause errors.
An important example of such integrated systems are memory devices. A read cycle in a nonvolatile memory is characterized by pointing to a new memory location, reading the new data and outputting the new data. In standard memory devices the reading of the new data and the outputting of it takes place at different times. This effects the noise spikes and can be controlled in a relatively easy manner.
In contrast, in an interleaved memory the problem is more severe because each output buffer is slaved to distinct banks of the memory that alternately convey new read data. Through an internal common data bus, the control circuits of a bank transfer the new read data towards the output circuits, so the reading of the data may take place at the same time the previously read data (from a different bank) is being output. This makes the problems represented by the output switching noise more critical.
Naturally, a similar situation may be present in any integrated digital system in which there are two or more asynchronous sources of data that must be functionally conveyed. For example, in an interleaved manner, the data is conveyed towards a single output register driving a single buffer (serial output stream) or an array of buffers (parallel output stream).
The amplitude of the switching noise spikes can be reduced, according to a conventional technique, by limiting the maximum current absorbed by a buffer or an array of buffers while switching the output, but this approach slows down the speed of the system. Consequently, there is a need for a circuit that would allow for a reduction of the switching noise without sensibly incrementing the time of response of the integrated system.
In view of the foregoing background, it is an object of the present invention to provide a pre-charging circuit for an output buffer that, by varying the voltage on the load capacitance of the buffer in the time interval that precedes the loading in the output buffer of a new logic value different from the current one, realizes less abrupt transitions. This reduces the switching noise.
This and other objects, advantages and features are obtained by the pre-charging circuit that, immediately before the instant in which the new logic value is produced on the output node, connects an internal, pre-charged capacitor at a certain voltage, in parallel to the load capacitance of the output node of the buffer.
Therefore, the transition of the output data starts from an intermediate voltage level. In this way the amplitude of noise peaks is reduced because current peaks of reduced amplitude occur in the same switching time interval.
In particular, the pre-charging circuit preferably comprises an internal capacitance, and a pass-gate connected between the output node and the internal capacitance for connecting the internal capacitance in parallel to the load capacitance, and a driver connected to the internal capacitance for charging thereof to a voltage level between a voltage level of the new data and a voltage level of a logic inversion of current data being output.
The digital system may comprise an output data register connected to the output buffer. The digital system generates a first pulse for enabling output of the new data and a second pulse for loading the new data in the output data register. The second pulse may have a duration less than a duration of the first pulse.
The pre-charging circuit preferably further comprises a first pass-gate connected between the output data register and the output buffer for enabling output of the new data based upon the first pulse. The driver may be disabled based upon the first pulse.
The pre-charging circuit preferably further comprises a first logic gate having a first input for receiving the new data and a second input for receiving the current data being output, and a second logic gate having a first input for receiving the second pulse and a second input for receiving an output signal from the first logic gate. In one embodiment, the first logic gate may be an XOR logic gate, and the second logic gate may be an AND logic gate.
The pre-charging circuit preferably further comprises a recovery register connected to the driver, and a second driver connected to the recovery register and being disabled by the first pulse. The second driver is for charging the recovery register with the current data being output. The digital system preferably further comprises a multiplexer coupling an output of the recovery register to an input of the driver based upon an external command signal.
The digital system preferably further comprises a logic gate connected to the output buffer, wherein the logic gate enables the output buffer based upon a pair of external command signals.